YOUR EXPERT PARTNER IN ASIC DIGITAL DESIGN
ASIC DESIGN
- Top Level Infrastructure
- Module Development
- Memory Subsystems
- Bus Architectures
- Register Maps
- Interfaces & Protocols
SOLUTIONS
- Bug Fixes / ECO
- Reverse Engineering
- Area Reduction
- Code Analysis & Rework
- Redesign for Safety
- Redesign for Test
FPGA DESIGN
- ASIC/FPGA Co-design
- FPGA Environments
- ASIC to FPGA flow
- PCB Development
- Analog Emulation
- User Interfaces
REDESIGN
- Get Feature Complete
- Smaller Equivalent Functions
- Scan Insertion from Scratch
- Improvement of Scan Coverage
- Design or Upgrades to ISO26262
- Recovering Legacy Code for Reuse